1. Field of the Invention
The present invention relates to a method for defect diagnosis, and particularly to a method for defect screen and sample.
2. Description of Prior Art
The fabrication process for integrated circuit dice includes film deposition, masking, photo lithography, etching, etc. During the fabrication process, the random particle defect and systematic defect are affecting the product yield. The product yield is related to the die cost.
As the feature size of the design layout shrinks, the product yield relevant defects become smaller. Fab has to increase the sensitivity of a scan and inspection tool in order to capture all killer defects on the wafer. As a result, the number of detected defects may increase and the percentage of non-killer defects may be higher. Further, when a scanning electron microscope (SEM) review tool is used to observe and classify all killer defects in order to determine a potential clue, a limited time in the fab and Review SEM capacity may restrict review sampling count per wafer. Consequently, it may be difficult to identify a defect of interest type that should be monitored in production and have increased risk of missing the killer defects.
Without a quick and innovative method to identify systematic defect early, fab may suffer larger yield loss and take longer learning curve cycle time toward volume production.